1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices and, in particular, to a process module that produces DMOS devices with highly controllable parameters and allows DMOS transistors to be incorporated into a CMOS-based fabrication process flow without disturbing existing CMOS/E.sup.2 PROM devices.
2. Discussion of The Related Art
Two distinct types of DMOS structures are known: vertical DMOS (VDMOS), and lateral DMOS (LDMOS). FIGS. 1A and 1B show cross-sectional views of VDMOS and LDMOS devices 100 and 100' respectively.
Both VDMOS structure 100 and LDMOS structure 100' include a P type body region 116 formed within an N type tub 106. N type source region 118 is formed within P type body 116.
An N type drain region is formed within the surrounding silicon. In the case of VDMOS structure 100, the drain takes the form of buried N+ layer 102 which is in electrical communication with sinker region 108 having sinker contact 108a. In the case of LDMOS structure 100', the drain takes the form of the surrounding N tub 106 having contact region 107.
Channel 105 lies between the source and drain. Gate 112 overlies channel 105 and is separated from the channel by gate oxide 110.
DMOS devices 100 and 100' are electrically isolated from surrounding structures by adjacent P type well 150, buried P layer 152, and field oxide 104.
DMOS transistors require the N-source to be self-aligned to the P-body implant in order to yield good threshold voltage (V.sub.t) and "on" drain-source resistance (R.sub.ds.sbsb.--.sub.on) control characteristics. This is typically accomplished by 1) implanting the P-body after the DMOS polysilicon has been defined, 2) driving-in the P-body implant with a large thermal budget that produces a large diffusion length (.sqroot.Dt), and then 3) implanting the N-source. The DMOS channel length (L.sub.D) is defined as the length of lateral extension of the P-body region under the polysilicon gate. A conventional process flow for fabricating a VDMOS structure is illustrated in greater detail in FIGS. 2A-2D.
FIG. 2A shows a precursor VDMOS structure 101 created within epitaxial silicon 103 grown over P-silicon substrate 156. Precursor VDMOS structure 101 includes N.sup.+ buried layer 102 formed by implantation into substrate 156 followed by growth of epitaxial layer 103. N-tub region 106 and N-sinker region 108 are then defined using N-tub and N-sinker masks, respectively. Field oxide isolation regions 104 are defined with an additional field oxide region 104' providing isolation for the N.sup.+ sinker region 108. A layer of gate oxide 110 separates the polysilicon gate regions 112 from the N-tub 106.
FIG. 2B shows the formation of a photoresist mask 114 over selected portions of precursor VDMOS structure 101. Resist mask 114 is used to facilitate a boron implant for initial introduction of P-type dopant for the P-body region.
FIG. 2C shows the P-body region 116 of the VDMOS device following thermal drive-in. FIG. 1D shows the final VDMOS device structure after a mask and ion implant step to define N-source regions 118.
The channel length of the VDMOS device shown in FIG. 2D is designated as L.sub.D. In this DMOS design, channel length L.sub.D is not affected by mask misalignments or etch biases. This is because both the P-body implant and the N-source implant are self-aligned to polysilicon gates that have already been formed.
Recent circuit applications require DMOS structures to be fabricated on the same chip as E.sup.2 PROM devices. Cross-sectional views of a conventional E.sup.2 PROM structure are shown in FIGS. 3A and 3B.
It is desirable to use the same polysilicon layer for both the E.sup.2 PROM floating gate and for the DMOS polysilicon gate. However, in processes utilized to manufacture the E.sup.2 PROM structure shown in FIGS. 3A-3B, the thermal budget cannot be too high following deposition of the floating polysilicon gate or else the double diffused drain (DDD) and high voltage threshold voltage (HV.sub.t) implants, created prior to deposition of the floating polysilicon, will be adversely affected.
Specifically, application of too high a thermal budget will disturb the DDD and the tunnel oxide will be degraded. That is, if a large thermal budget is run after formation of the floating gate polysilicon structure, then the DDD implant will diffuse too deeply beyond the typically desired 0.4 .mu.m depth. In such a process flow, HV.sub.t implant would also diffuse deeper, changing the threshold voltage of the device. Thus, the presence of an E.sup.2 PROM structure requires that the thermal budget be kept relatively low once the floating polysilicon gate has been deposited.
However, as described in connection with FIG. 2C above, the conventional DMOS process flow requires that heat cycles be sufficiently high following deposition of the polysilicon gate in order to drive the P-body implant approximately one micron laterally.
One solution to this incongruity between E.sup.2 PROM and DMOS process flow requirements is to utilize separate polysilicon layers for the gate of the DMOS and for the floating gate of the E.sup.2 PROM. However, this approach increases the number of processing steps, and thus increases wafer cost and defect density.
Moreover, utilizing separate polysilicon layers can introduce a "poly stringer" problem into the process. This "poly stringer" problem is a result of the second polysilicon deposition occurring over the sharp steps of the masked and defined first polysilicon layer. Such a structure is difficult to etch without leaving second polysilicon filaments.
Another solution to the problem is proposed in pending U.S. patent application Ser. No. 08/870,970, filed Jun. 6, 1997, entitled "DMOS PROCESS MODULE APPLICABLE TO AN E.sup.2 CMOS CORE PROCESS," inventor Douglas R. Farrenkopf (hereafter "the Farrenkopf Application"). The Farrenkopf Application describes a process module in which the P-body implant and the N-source implant of a DMOS device are self-aligned by employing the composite nitride layer which has already been used to form field isolation structures.
FIGS. 4A-4J illustrate cross-sectional views of a process flow for fabricating a DMOS transistor structure in an E.sup.2 PROM process flow in accordance with the Farrenkopf Application.
FIG. 4A shows precursor VDMOS structure 201, which is the starting point for the Farrenkopf process. Precursor VDMOS structure 201 is formed in a conventional manner within epitaxial silicon 203 grown over silicon substrate 256. Precursor VDMOS structure 201 includes an N-type tub 204 formed over an N+ buried region 202. N-type tub 204 includes an N+ sinker region 208. N+ sinker region 208 is formed at an edge of N-type tub 204 and extends from a surface of the N-type tub to the N+ buried region 202.
Referring now to FIG. 4B, a composite pad oxide 212 and nitride 214 deposition is performed upon precursor VDMOS structure 201, followed by definition of a composite mask and etching of the composite nitride layer to identify field oxide regions. A P-field mask and implant and is then performed to increase the P-well field threshold voltage. Field oxide isolation regions 216 are then grown in the conventional manner, resulting in the structure shown in FIG. 4B.
Next, as shown in FIG. 4C, a layer of resist 218 is formed and the nitride 214 is etched using this P-body mask 218, enabling a subsequent implant of P-type dopant to form a P-body region 220 in the N-tub 204.
Following removal of the P-body mask 218, another layer of resist 222 is formed and patterned to enable another P-type implant to form a deep P+ region 224 within the P-body 220, resulting in the structure shown in FIG. 4D.
In FIG. 4E, the deep P+ resist mask 222 is then stripped and a P-body thermal drive-in step is performed. The application of thermal energy results in the additional growth of oxide during this step. Approximately 400 .ANG. of oxide 212 remains over the P-body region 220, so that silicon is not reached during the subsequent stripping of the composite nitride 214 as shown in FIG. 4G strip step.
In FIG. 4F, ion implant of N-type dopant is then performed, resulting in formation of an N-source region 226 in P-body 220. Nitride layer 214 should be thick enough to block the N-source implant at the periphery of the P-body region 220, but if it isn't, an additional nitride deposition step could be inserted before the P-body mask step described above.
In FIG. 4G, following a nitride strip and pad oxide strip, a layer of sacrificial oxide is grown. Then, a threshold voltage V.sub.T adjust mask is defined to cover the VDMOS region with resist. A V.sub.T implant is then performed to set the threshold voltages of the MOS devices to an appropriate level. The sacrificial oxide is then stripped.
A screen oxide layer is then grown, and a buried N+ mask is formed, followed by a buried N+ implant. The screen oxide is then stripped and a cell gate oxide layer is formed. Next, a tunnel oxide mask is patterned, tunnel oxide windows are etched in the gate oxide and tunnel oxide is grown in the windows. A layer of polysilicon is then deposited and doped to a desired conductivity level. A layer of oxide/nitride/oxide (ONO) is then formed on the polysilicon layer.
The polysilicon layer is then masked and etched to define the polysilicon gate regions 230 of the VDMOS transistor. Simultaneously, the polysilicon floating gates of the E.sup.2 PROM devices are also being created. The resulting VDMOS structure is shown in FIG. 4H.
Referring to FIG. 4H, a threshold voltage implant for the low voltage devices is then performed, E.sup.2 PROM control gates are masked and implanted and a second gate oxide layer is grown. Next, the second layer of polysilicon for the E.sup.2 PROM is deposited, doped, masked and etched and a polyseal oxide is formed. Next, for the E.sup.2 PROM, the PLDD mask and implant and NLDD mask and implant steps are performed. Then, a spacer oxide is deposited and etched back to form oxide sidewall spacers 232 on the DMOS gate regions, as shown in FIG. 4I.
Then, an N+ mask is formed and N-type dopant is implanted into the VDMOS structure, forming N+ contacts 234 of N source regions 226, and also concentrated sinker contact 208a. Following a poly oxide step, a P+ mask is formed and P type dopant is implanted to form P+ region 235 separating N+ contact regions 234, as shown in FIG. 4J.
Fabrication of the VDMOS structure is completed with back-end processing, wherein a layer of dielectric material is formed, masked and etched to form contact openings to the VDMOS N source contact regions and the N+ sinker region. This is followed by deposition, masking and etching of a first metal layer to form contacts to the N source contact and N+ sinker regions. Contacts and metal are also connected to the gate structure.
One important result of the approach proposed by the Farrenkopf Application is that the channel length L.sub.D of the DMOS device is self-aligned to the composite nitride, and is not dependent upon masking alignments or etch biases.
There are two important reasons why the channel length L.sub.D must be well controlled. First, in a DMOS transistor, the threshold voltage is determined by the P-body concentration in the proximity of the N.sup.- source. If there is misalignment between the source and the P-body, even on the order of 0.1 .mu.m, this will result in large threshold voltage variations. Second, R.sub.ds.sbsb.--.sub.on is affected by channel length L.sub.D ; therefore, variations in channel length L.sub.D result in unwanted and unpredictable changes in Rd.sub.ds.sbsb.--.sub.on.
It is important to note that while the channel length L.sub.D of the DMOS device is self-aligned, the same cannot be said for the length of the gate overlap of the source (L.sub.S). This is because the position of polysilicon gate relative to the source is determined by masking steps.
Fortunately, precise control of L.sub.S is not critical to a DMOS transistor. This is because the L.sub.S would affect the DMOS transistor negatively only if it became so long as to significantly increase the source resistance. However, in the process flow proposed by Farrenkopf the gate/source overlap L.sub.S only increases source resistance to the extent that total Rd.sub.ds.sbsb.--.sub.on increased by less than one percent, which is insignificant.
While the process proposed by the Farrenkopf Application provides for significant improvement over the prior art, it does have one drawback. It has proven relatively difficult to remove composite nitride layer 214 relative to the underlying pad oxide as called for in FIG. 4G. The aggressive nature of the composite nitride strip after the N-source implantation leads to large oxide overetch, despite the presence of the additional .apprxeq.400 .ANG. of oxide grown resulting from the P-body drive-in step of FIG. 4E. Because of overetching during removal of composite nitride, the silicon surface is unprotected and trenches form in the silicon of the P-body and N-source during the nitride strip. The resulting loss in dopant at the P-body and N-source is detrimental to device behavior and, thus, to process control.
Therefore, it is desirable to utilize a process flow wherein the composite nitride layer is removed prior to performance of the P-body and N-source implants, while retaining the self-aligned channel overlap and overall process simplicity of the Farrenkopf process.